1. Field of the Invention
The present invention relates to a semiconductor memory which lowers a DC source voltage supplied from outside to a value equal to a reference voltage and supplies the thus lowered power source to a selected internal circuit.
2. Description of the Related Art
The capacity of semiconductor memories now doubles every three years, papers on 16 megabit DRAMs have already been read at academic societies and samples of such DRAMs are expected on the market in the near future. Although the research and production of miniaturized elements has been developed to achieve such memory capacity, the source voltage to be supplied to the memory remains unchanged at 5 volts.
The reliability of semiconductor memories sometimes becomes deteriorated, if the source voltage is supplied unchanged, even if there is a decreased characteristic of the memory such as lower voltage proofness at some portion thereof due to the increased miniaturization of the elements. Further, there is possibility of accelerated deterioration of reliability of the elements which may be caused by a temperature rise resulting from increased power consumption of the elements. As a means to solve this problem, there has recently been a movement in the industry to provide an internal voltage-down-converter to decrease an operating voltage of the internal circuit while receiving the external source voltage unchanged as is.
By decreasing the operating voltage of the internal circuit, the electric field applied to the internal circuit is weakened. Concurrently, the temperature rise of the circuit can be controlled due to a drop in power consumption, so that decreasing the operating voltage is an effective means to improve the reliability of the circuit. However, since the operating speed of the circuit decreases as the operating voltage decreases, the above method has a drawback when applied to a semiconductor memory which requires both high capacity and high operating speed of the element.
For the purpose of retaining the advantages resulting from a lower operating voltage while retaining the moderate operating speed of the overall semiconductor element, a selected portion of the internal circuit is arranged to operate with a lower voltage. Based on the above, optimum conditions have been obtained to achieve both sufficient reliability and high speed performance of the semiconductor memory.
As an example of methods applied to semiconductor memories, there is the method that a memory cell portion of the semiconductor memory is operated by a lowered voltage to protect against possible deterioration of the reliability of the portion which may be caused by thin films applied thereto to increase capacity, and other circuits of the memory are operated by the external source voltage.
FIG. 1 is a diagram showing the operation characteristic of an example of a voltage-down-converter (not shown) devised so as to be incorporated in this type of semiconductor memory, wherein the lateral axis represents an external source voltage and the vertical axis an internal source voltage. The operation of the voltage-down-converter will be described with reference to FIG. 1. The internal source voltage which is equal to the output voltage of the voltage-down-converter keeps a predetermined voltage (a standard internal voltage) 3.3 V during a normal operation. Therefore, the internal source voltage increases as the external source voltage increases until the external source voltage reaches 3.3 V. When the external source voltage exceeds 3.3 V and increases to 6 V, the internal source voltage holds a predetermined value of 3.3 V. When the external source voltage increases over 6 V, the internal source voltage also increases in accordance with the increase of the external source voltage.
In the above voltage-down-converter, an increase of the external source voltage over 6 V results in an increase of the internal source voltage over the predetermined value to effectively perform a burn-in test in screening for removing initial defects. A burn-in test is a method for removing initial defects in a reduced time by detecting defects generated at an accelerated rate by operating the memory under a high temperature environment and by applying a higher voltage thereto. However, with the structure of the memory wherein the selected portion of the internal circuit is operated by the above voltage-down-converter, since the internal source voltage obtained through a voltage drop is applied to the portion, a voltage corresponding to a higher voltage supplied from outside by the burning test is not applied to the internal circuit, thereby resulting in failure to accelerate the detection of defects. Therefore, the memory of the present invention is arranged to have the characteristic of increasing the internal source voltage only at the time of the burn-in test when a high external source voltage is applied.
Conventional semiconductor memories incorporating a voltage-down-converter with the above characteristic have the drawback that memories with a small margin against source voltage variation are sometimes shipped without being detected by the source-voltage-margin-test which is performed by varying the external source voltage (usually 4.0 to 6.0 V) before shipment. The reason is described below.
Generally, since it is necessary to guarantee at the time of shipment of semiconductor devices including memories, that the product satisfies the characteristics listed in specifications, various tests are performed before shipment. The most important parameter which influences all of the characteristics in the above tests is the source voltage. In the case that the rated source voltage of the product is 5 V (D C), the product is normally guaranteed against various characteristics under the applied external source voltage in the range of 5.0 V+-10%. Consequently, all of the characteristics of the product are required to be satisfied for the source voltage in the range of 4.5 to 5.0 V, but the actual test is performed with a safety margin for the source voltage in the range of 4.0 to 6.0 V. However, in a semiconductor memory incorporating the above voltage-down-converter, a constant voltage lowered by the voltage-down-converter is supplied to the internal circuit even if the external source voltage is varied in the range of 4.0 to 6.0 V, so that no source margin test of the internal circuit can actually be performed. This gives the user the false impression that the product has an extraordinarily sufficient stable margin against variation of the source capacity to the great advantage of the overall characteristics of the product. However, this results in the following problem for the maker which ships the product.
In other words, even if supplied by the voltage-down-converter, voltages to be supplied to the internal circuit often vary according to variations in the external source voltage or the influence of noises. In particular, variations due to noise are unpredictable. It is difficult to test in advance. Therefore, with the conventional test method, there is the possibility of shipping products whose internal circuits have only a small margin for operation voltage, which may cause defective operation when the internal source voltage varies due to the influence of noise in actual operation.
In order to prevent this problem, even if the semiconductor memory is so structured as to supply a constant low voltage to a portion of the internal circuit of the memory from the voltage-down-converter, it is further necessary to provide the portion of the internal circuit with a sufficient operational margin against variations in the source voltage. In other words, power source voltages higher or lower than the predetermined voltages should be applied to the internal circuit which is designed to receive the predetermined voltage, and testing performed to remove products with small operational margins during pre-shipment testing as defective.
To meet the above purpose, the operational margin of the internal circuits of conventional semiconductor memories can be tested against source voltage variations, if the rising characteristic of the lower voltage and higher voltage sides of the voltage-down-converter characteristic shown in FIG. 1 are utilized.
However, in order to perform a performance test with this method, it is necessary to increase or decrease the external source voltage more than is normally required. For example, if the characteristic of the voltage-down-converter is as shown in FIG. 1, then the external source voltage must be changed in the range of 3.0 to 6.3 V to perform a test in the range of 3.0 to 3.6 V against the voltage of 3.3 V of the voltage-down-converter.
Although this test condition offers no problem for circuits which are supplied with a source voltage from the voltage-down-converter, the voltage is too high for other circuits operated by the external source voltage, so that it cannot be said to be an appropriate test condition.